1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a multi-port semiconductor memory device.
2. Description of Related Art
FIG. 5 is a schematic view for explaining a memory cell of a dual-port RAM having eight transistors per memory cell. With reference to FIG. 5, the memory cell includes inverters INV1 and INV2. The input of the inverter INV1 is connected to the output of the inverter INV2, while the output of the inverter INV1 is connected to the input of the inverter INV2. Additionally, the memory cell includes access transistors 111 and 112 for a port A and access transistors 113 and 114 for a port B between connection nodes N1 and N2 and bit lines DTA/DBA and DTB/DBB, respectively. This memory cell is a memory cell of an SRAM (a static RAM) which can be simultaneously accessed through the port A and the port B. When a word line WLA is activated, data write or data read from the bit line pair DTA and DBA can be carried out. When a word line WLB is activated, data write or data read from the bit line pair DTB and DBB can be carried out. Data stored in the memory cell is latched by the inverters INV1 and INV2. In order to store data in the memory cell through the port A when the voltage on the bit line DTA is high level and the voltage on the bit line DBA is low level, the word line WLA is activated and output voltages of the inverters INV1 and INV2 are the low level and the high level, respectively. After that, when the memory cell stores inverted data through the port A or through the port B, the two inverters invert the stored data. For example, when output voltage of the inverters INV1 and INV2 are the low level and the high level, respectively, and the word line WLA is activated and data expressed by the low level on DTA and the high level on DBA is written, output voltages of the inverters INV1 and INV2 are the high level and the low level, respectively.
FIG. 6 is a view for explaining a structure and operation of the memory cell of FIG. 5. FIG. 6 shows a PMOS transistor PM1 a source of which is connected to a power supply, an NMOS transistor NM1 a source of which is connected to GND and a drain of which is connected to a drain of the PMOS transistor PM1, a PMOS transistor PM2 a source of which is connected to the power supply, and an NMOS transistor NM2 a source of which is connected to GND and a drain of which is connected to a drain of the PMOS transistor PM2. A common gate of the PMOS transistor PM1 and the NMOS transistor NM1 is connected to a common drain of the PMOS transistor PM2 and the NMOS transistor NM2, while a common drain of the PMOS transistor PM1 and the NMOS transistor NM1 is connected to a common gate of the PMOS transistor PM2 and the NMOS transistor NM2. The common drain of the PMOS transistor PM1 and the NMOS transistor NM1 is connected to the bit lines DTA and DTB through access transistors 111 and 113 gates of which are connected to the word lines WLA and WLB, respectively. The common drain of the PMOS transistor PM2 and the NMOS transistor NM2 is connected to the bit lines DBA and DBB through access transistors 112 and 114 gates of which are connected to the word lines WLA and WLB, respectively.
FIG. 6 schematically illustrates a state where the word lines WLA and WLB are activated to be high, the access transistors 111-114 are turned on, and the bit lines DTA and DTB precharged to the high level is discharged through the NMOS transistor NM1. Cell currents Icell_A and Icell_B flow through the access transistor (port A access Tr) 111 and the access transistor (port B access Tr) 113, respectively, into the drain and ultimately into the source of the NMOS transistor NM1.
With regard to the structure of a dual-port RAM or a multi-port RAM, please also refer to, for example, Japanese Patent Application Laid-open No. Hei 5-299621 and Japanese Patent Application Laid-open No. 2005-346837. Japanese Patent Application Laid-open No. Hei 5-299621 discloses a dual-port RAM where, in order to increase the integration degree, the access transistors are formed of PMOS transistors. Japanese Patent Application Laid-open No. 2005-346837 discloses a dual-port RAM where, in reading operation, when it is detected that row addresses of first and second ports match each other, only a word line of the first port is activated, a column switch connects a bit line pair of the first port selected according to a column address of the first port to a data line pair of the first port and connects a bit line pair of the first port selected according to a column address of the second port to a data line pair of the second port.
The present inventor has recognized that, in the dual-port RAM of FIG. 5, when simultaneous access where word lines WLA and WLB are simultaneously activated is made, bit line potential changes at a lower speed than that in a case where access is made only through one of the ports. Then the access time is increased or malfunction is caused. The following is a study made by the present inventor.
In the dual-port RAM of FIGS. 5 and 6, both of the access transistors provided correspondingly to the bit lines of the two ports, respectively, are connected to an output of one inverter. Therefore, when the word lines WLA and WLB are simultaneously activated, current flowing through one access transistor is decreased. Further, depending on variations in current driving ability of the access transistors or the like, the amount of current flowing through an access transistor is, for example, on the order of ⅓ to 1/10 of that when simultaneous access is not made. Therefore, amplitude of the bit line potential when the port A and the port B are simultaneously accessed is decreased.
Further, with the progress of miniaturization of semiconductor devices, random variations in the cell currents Icell_A and Icell_B of the port A and the port B in one memory cell increases accordingly. FIG. 7B illustrates an equivalent circuit of FIG. 7A including access transistors 111 and 113 and an NMOS transistor NM1.
In FIG. 7A, variations in the cell currents Icell_A and Icell_B is variations in currents IAccA and IAccB in the equivalent circuit in FIG. 7B. RAccA and RAccB are on-resistances of the access transistors of the port A and the port B, and RDRV is on-resistance of the NMOS transistor NM1 (driver transistor) of an inverter in the memory cell.
IAccA+IAccB=IDRV, and therefore, when the current IAccA flowing through one access transistor increases, the current IAccB flowing through the other access transistor decreases. This current difference causes the difference in discharging rate of the bit lines. More specifically, variations in the cell currents Icell_A and Icell_B are found to be variations in discharge ability based on current driving ability of the access transistors. When the difference in discharging rate is remarkable, potential difference between a pair of bit lines of one port is decreased, which may cause malfunction. In order to prevent such malfunction, it is necessary to enhance current driving ability of the driver transistor. However, enhancing the current driving ability of the driver transistor increases the memory cell area.
FIG. 8 is a waveform chart schematically illustrating relationship between presence and absence of variations in the access transistors of the port A and the port B and data on the bit lines. Variations in current driving ability of the access transistors drastically decrease current flowing through the access transistor with the lower current driving ability. Therefore, potential difference between a bit line pair (in FIG. 8, the bit line pair DTA/DBA) is decreased.
As a result, there is a problem that variations in access transistors between ports decrease potential difference between a bit line pair, which causes unstable operation of a sense amplifier to cause false sensing.